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Design of a Fully Integrated VHF CP-PLL Frequency Synthesizer with an All-Digital Defect-Oriented Built-In Self-Test.

Article scientifique 2022 Anglais

Résumé

Abstract This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40 to 100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of -132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6µ complementary metal oxide-semiconductor process.

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Kommey, B., Addo, E., Yankey, J., Agbemenu, A., Tchao, E., Yeboah‐Akowuah, B. (2022). Design of a Fully Integrated VHF CP-PLL Frequency Synthesizer with an All-Digital Defect-Oriented Built-In Self-Test.. https://doi.org/10.21203/rs.3.rs-1231062/v1

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Auteur(s)

Benjamin Kommey Ernest Ofosu Addo Jepthah Yankey Andrew Selasi Agbemenu Eric Tutu Tchao Bright Yeboah‐Akowuah

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